Power management granularity and power state exit latencies are affected by lock time of a phase locked loop (PLL). One way to speed up lock time for a PLL is to apply lookup tables (LUTs) that store PLL signal conditions for fast lock. However, such traditional uses of LUTs continue to exhibit long phase lock times (e.g., 40-100 reference cycles). A power management controller may save power by clock gating, and to some extent by shutting down PLLs when they are not in use. However, a limiting factor to the power reduction from power management of the clocking of the whole system is the latency of the power on of PLLs. As processors are expected to operate in various power states (e.g., sleep, idle, normal, etc.), moving from one power state to another may cause the PLL to re-lock, which takes time and power.